Mikaël Briday
Maître de conférences -- Assistant Professor

IRCCyN - UMR CNRS 6597
1, rue de la Noë
B.P. 92101
44 321 Nantes Cedex 3
France

e-mail : nospam_mikael.briday@irccyn.ec-nantes.fr (remove nospam_)

Access: Research | Teaching | Publications
Research

Hardware Architecture Description Language

The objective of Harmless is to model the hardware architecture (processor and peripherals) of real-time embedded systems. An Harmless compiler is also designed to generate a simulator from a description.

Two simulation approaches are attractive: The first approach consists of an Instruction Set Simulator (ISS) that takes only the instruction behavior into account independently of the time needed to execute the instruction. The second approach is based on a Cycle-Accurate Simulator (CAS) which takes into account the instruction behavior and the timing of the real system (it models the internal architecture). The internal pipeline model is based on finite state automaton for simulation efficiency.

I started to work on this topic in 2005 with Jean-Luc Béchennec. It was supported by the MasCotTe project (ANR Predit). Rola Kassem defended its PhD thesis on 2010

This work is now supported by the ANR RESPECTED which aims to model a multi-core architecture and take into account thermal effects on the processor model. Future works include performance improvement(compiled simulation), superscalar processor description and peripherals modelling.

Operating System

This topics, driven by Jean-Luc Béchennec, is focused on the mature operating system Trampoline, based on the OSEK/VDX and AutoSar standards.

This work is supported by the ANR RESPECTED to add multi-processor capability and other scheduling policies implementation.

Teaching

I am teaching at IUT de Nantes, in dept Génie électrique et Informatique Industrielle and in Licence Pro SEICOM.

Main teaching topics

  • control systems
  • projets (design, implementation of small embedded systems)
  • Digital electronics
  • Industrial data processing (Infineon C167, Atmel AVR, ..)
  • real time systems (using the Open Source Trampoline RTOS)
  • Embedded systems (embedded Linux)
Publications

International Journal papers

[KBBST-JSA-12]
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton and Yvon Trinquet. Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation. Journal of Systems Architecture (JSA), Volume 58 - n° 8/2012, pages 318 to 337Abstract, BibTeX, pdf, HAL.
Validation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets.
%% hal-00768517, version 1
%% http://hal.archives-ouvertes.fr/hal-00768517
@article{kassem:hal-00768517,
hal_id = {hal-00768517},
url = {http://hal.archives-ouvertes.fr/hal-00768517},
title = {{Harmless, a Hardware Architecture Description Language Dedicated to Real-Time Embedded System Simulation}},
author = {Kassem, Rola and Briday, Mika{\"e}l and B{\'e}chennec, Jean-Luc and Savaton, Guillaume and Trinquet, Yvon},
abstract = {{Validation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's software using an accurate model of the processor resides in the development of a handwritten simulator which is a difficult and tedious task. This paper presents Harmless, a hardware Architecture Description Language (ADL) that mainly targets real-time embedded systems. Harmless is dedicated to the generation of simulator of the hardware platform to develop and test real-time embedded applications. Compared to existing ADLs, Harmless1) offers a more flexible description of the Instruction Set Architecture (ISA) 2) allows to describe the microarchitecture independently of the ISA to ease its reuse and 3) compares favorably to simulators generated by the existing ADLs toolsets.}},
keywords = {Hardware architecture description language; Instruction set simulation; Cycle-accurate simulation},
language = {Anglais},
affiliation = {Beirut Arab University - bau , Institut de Recherche en Communications et en Cybern{\'e}tique de Nantes - IRCCyN , Ecole Sup{\'e}rieure d'Electronique de l'Ouest - ESEO},
pages = {318-337},
journal = {Journal of Systems Architecture},
volume = {58},
number = {8 },
audience = {internationale },
doi = {10.1016/j.sysarc.2012.05.001 },
year = {2012},
month = Sep,
pdf = {http://hal.archives-ouvertes.fr/hal-00768517/PDF/main.pdf},
}
[BBT-JESA-06]
Mikaël Briday, Jean-Luc Béchennec and Yvon Trinquet. ReTiS: A Real-Time Simulation platform. Journal Européen des Systèmes Automatisés (JESA), Volume 40 - n° 8/2006, pages 819 to 846Abstract, BibTeX.
This paper presents ReTiS, a simulation tool for distributed real-time application analysis. Simulation concerns the operational architecture and takes into account the software (executable code of real-time tasks and real-time operating system) and the hardware (set of processors and networks). In this paper we present two mechanisms. The first enables the tracking of data dependencies across a distributed system. The second permits the detection of task switching and the analysis of a task's stack (usage and corruption). These mechanisms do not rely on a particular hardware or operating system nor do they require any application or operating system code modification. We show their interest for the analysis of the temporal behaviour of real-time applications in a distributed system.
@article{BBT-JESA-06,
Author = {Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
Journal = {Journal Europ{\'e}en des Syst{\`e}mes Automatis{\'e}s (JESA)},
Number = {8},
Pages = {819 to 846},
Title = {ReTiS: A Real-Time Simulation platform.},
Volume = {40},
Year = {2006}}

International Conference papers

[SBBFP-SIES-16]
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement. Hardware runtime verification of embedded software in SoPC. In IEEE International Symposium on Industrial Embedded Systems (SIES 2016), Cracovie, Poland, 2016.Abstract.
This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a micro-controller and a FPGA. The goal is to verify at runtime that the execution of the software on the micro-controller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesised from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formulas.
[MBBF-WCET-16]
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou. BEST: a Binary Executable Slicing Tool. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016), Toulouse, France, 2016.Abstract.
We describe the implementation of \best, a tool for slicing binary code. We aim to integrate this tool in a WCET estimation framework based on model checking. In this approach, program slicing is used to abstract the program model in order to reduce the state space of the system. In this article, we also report on the results of an evaluation of the efficiency of the abstraction technique.
[TBBR-SIMULTECH-14]
J. Tanguy, J.-L. Béchennec, M. Briday, and O.H. Roux. Reactive embedded device driver synthesis using logical timed models. In The 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), Vienna, Austria, 2014.Abstract, BibTeX, pdf.
The critical nature of hard real-time embedded systems leads to an increased usage of Model Based Design to generate a correct-by-construction code from a formal specification. If Model Based Design is widely used at application level, most of the low level code, like the device drivers, remains written by hand. Timed Automata are an appropriate formalism to model real time embedded systems but are not easy to use in practice for two reasons i) both hardware and software timings are difficult to obtain, ii) a complex infrastructure is needed for their implementation. This paper introduces an extension of untimed automata with logical time. The new semantics introduces two new types of actions: delayed action which are possibly avoidable, and ineluctable action which will happen eventually. The controller synthesis problem is adapted to this new semantics. This paper focuses specifically on the reachability problem and gives an algorithm to generate a controller.
@inproceedings{TBBR-SIMULTECH-14,
Author = {Julien Tanguy and Jean-Luc B{\'e}chennec and Mikael Briday and Olivier H. Roux},
Booktitle = {The 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH 2014), Vienna, Austria},
Editor = {Scitepress Digital Library},
Month = {August},
Title = { Reactive embedded device driver synthesis using logical timed models},
Year = {2014}}
[BBBT-SIMUTOOLS-14]
A. Bullich, M. Briday, J.-L. Béchennec, and Y. Trinquet. Improving Processor Hardware Compiled Cycle Accurate Simulation Using Program Abstraction. In Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques (SIMUTOOLS'14), Lisbon, Portugal, pages 186¿194, 2013.Abstract, BibTeX, pdf.
Verification is an important step in the development of real-time embedded systems. The validation of a real-time system uses a timing accurate simulator and, when the actual binary code is used, a cycle accurate simulator (CAS). However, a CAS is slow especially when the simulated processor is complex and the application is big. One way to improve the speed of a CAS is to use compiled simulation. In this scheme, the application binary code model is merged with the processor model. This allows to remove operations from the simulator and to speed up it. In this paper, we show how to use an abstraction of the program and improve the handling of functions calls. The resulted simulator is temporally and functionally equivalent. This technique improves simulation speed by more than 50% over the speed of an interpreted CAS
@inproceedings{BBBT-SIMUTOOLS-14,
Author = {Adrien Bullich and Mika\"{e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
Booktitle = {Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques},
Doi = {10.4108/icst.simutools.2014.254792},
Isbn = {978-1-63190-007-5},
Keywords = {compiled simulation, cycle accurate simulation, processor hardware simulation, real-time systems},
Location = {Lisbon, Portugal},
Numpages = {9},
Pages = {186--194},
Publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)},
Series = {SIMUTools '14},
Title = {Improving Processor Hardware Compiled Cycle Accurate Simulation Using Program Abstraction},
Url = {http://dx.doi.org/10.4108/icst.simutools.2014.254792},
Year = {2014},
[BBBT-SIMUL-13]
A. Bullich, M. Briday, J.-L. Béchennec, and Y. Trinquet. Comcas : A compiled cycle accurate simulation for hardware architecture. In Fifth International Conference on Advances in System Simulation (SIMUL¿13), Venice, Italy, pages 137¿142, october 2013.Abstract, BibTeX, pdf.
Currently the development of embedded software managing hardware devices that fulfills industrial constraints (safety, real time constraints) is a very complex task. To allow an increased reusability between projects, generic device drivers have been developed in order to be used in a wide range of applications. Usually the level of genericity of such drivers require a lot of configuration code, which is often generated. However, a generic driver requires a lot of configuration and need more computing power and more memory needs than a specific driver. This paper presents a more efficient methodology to solve this issue based on a formal modeling of the device and the application. Starting from this modeling, we use well-known game theory techniques to solve the driver model synthesis problem. The resulting model is then translated into the actual driver embedded code with respect to an implementation model. By isolating the model of the device, we allow more reusability and interoperability between devices for a given application, while generating an application-specific driver.
@inproceedings{BBBT-SIMUL-13,
Author = {Adrien Bullich and Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
Booktitle = {Fifth International Conference on Advances in System Simulation (SIMUL'13), Venice, Italy},
Month = {october},
Pages = {137-142},
Title = {ComCas: A Compiled Cycle Accurate Simulation for Hardware Architecture},
Year = {2013}}
[TBBDR-ETFA-13]
J. Tanguy, J.-L. Béchennec, M. Briday, O. H. Roux, and S. Dubé. Device driver synthesis for embedded systems. In The 18th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2013), Cagliari, Italy, 2013. IEEE Computer Society Abstract, BibTeX, pdf.
Currently the development of embedded software managing hardware devices that fulfills industrial constraints (safety, real time constraints) is a very complex task. To allow an increased reusability between projects, generic device drivers have been developed in order to be used in a wide range of applications. Usually the level of genericity of such drivers require a lot of configuration code, which is often generated. However, a generic driver requires a lot of configuration and need more computing power and more memory needs than a specific driver. This paper presents a more efficient methodology to solve this issue based on a formal modeling of the device and the application. Starting from this modeling, we use well-known game theory techniques to solve the driver model synthesis problem. The resulting model is then translated into the actual driver embedded code with respect to an implementation model. By isolating the model of the device, we allow more reusability and interoperability between devices for a given application, while generating an application-specific driver.
@inproceedings{TBBDR-ETFA-13,
Address = {{C}agliari, {I}taly},
Author = {Tanguy, Julien and B{\'e}chennec, Jean-Luc and Briday, Mika\¨el and Roux, Olivier H. and Dub\'e, S\'ebastien},
Booktitle = {The 18th {IEEE} {I}nternational {C}onference on {E}merging {T}echnologies & {F}actory {A}utomation ({ETFA} 2013)},
Publisher = {{IEEE} {C}omputer {S}ociety},
Title = {Device driver synthesis for embedded systems},
Year = {2013}}
[SBBK-OCL-11]
Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday and Rola Kassem. An Architecture Description Language for Embedded Hardware Platforms Workshop on OCL and Textual Modelling (OCL 2011), July 2011Abstract, BibTeX, pdf.
Embedded software development relies on various tools (compilers, simulators, execution time estimators) that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain: significant benefits could be expected if they were automatically gen- erated from models expressed in a dedicated modeling language.
In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture De- scription Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set), resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions).
This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools fol- low the Model-Driven Engineering philosophy: metamodeling and model transfor- mations have been successfully applied to the automatic generation of processor simulators.
@inproceedings{SBBK-OCL-11,
Author = {Guillaume Savaton and Jean-Luc B{\'e}chennec and Mika{\"e}l Briday and Rola Kassem},
Booktitle = {Workshop on OCL and Textual Modelling (OCL 2011)},
Pages = {16},
Title = {An Architecture Description Language for Embedded Hardware Platforms},
Year = {2011}}
[BBA-SIES-11]
Jean-Luc Béchennec, Mikaël Briday and Valère Alibert.Extending Harmless Architecture Description Language for Embedded Real-Time Systems Validation6th IEEE International Symposium on Industrial Embedded Systems (SIES'11), June 2011.Abstract, BibTeX, pdf.
Harmless is a hardware architecture description language targeted to the simulation of embedded and real-time software. It allows to describe the instruction set and the micro-architecture of a processor. From this description, the Harmless compiler generates an Instruction Set Simulator and a Cycle Accurate Simulator. Both simulators are useful to test and validate embedded software and the latter is essential for Real-Time software. Their use is cheaper and more comfortable than the execution on the actual hardware. Moreover, with simulation, it is easy and unobtrusive to trace the execution and to report useful informations. However, tracing mechanisms may be difficult or even impossible to integrate without ad-hoc support in the simulator and, in our case, in the description of the processor.
This paper presents how Harmless is modified and used to add tracing support to simulators. This mechanism called action is used to extract high level information such has the task scheduling observation and stack safety analysis from the low level simulation. It also highlights how the Harmless description of a processor should be updated to support these features and applies it on three processors models.
@inproceedings{BBA-SIES-11,
Author = {Jean-Luc B{\'e}chennec and Mika{\"e}l Briday and Val{\`e}re Alibert},
Booktitle = {6th IEEE International Symposium on Industrial Embedded Systems (SIES'11)},
Month = {June},
Title = {Extending Harmless Architecture Description Language for Embedded Real-Time Systems Validation},
Year = {2011}}
[BBFPJ-SIMUTOOLS-10]
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin and Fabien Juif. ViPER: a lightweight approach to the simulation of distributed and embedded software 3rd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools'10 (acceptance rate 29%), March 2010Abstract, BibTeX, pdf.
This paper describes a simulation platform for embedded software named ViPER (Virtual Platform and Environment Runtime). ViPER is oriented toward (but not limited to) systems of the automotive domain. It allows to model and simulate distributed embedded hardware platforms in order to ease the early development stages of the embedded software.
Each node of the system is virtualized in a process that runs an ad-hoc port of the real-time operating system Trampoline. ViPER manages global time, hardware interrupt and offers a quick and easy way to model hardware devices. In order to close the loop, relevant parts of the environment can be simulated. Once a platform is modeled, ViPER generates description files for each node that ensure the conformance of the hardware abstraction layer to the virtual hardware. ViPER and Trampoline are available as free software.
@inproceedings{BBFPJ-SIMUTOOLS-10, Author = {Jean-Luc B{\e}chennec and Mika{\"e}l Briday and S{\'e}bastien Faucou and Florent Pavin and Fabien Juif},
Booktitle = {3rd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2010},
Month = {March},
Title = {ViPER: a lightweight approach to the simulation of distributed and embedded software},
Year = {2010}}
[KBBST-MESM-09]
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton and Yvon Trinquet. Cycle Accurate Simulator Generation Using HARMLESS. International Middle Eastern Multiconference on Simulation and Modelling (MESM'09), Eurosis, Beirut, Lebanon. September 2009Abstract, BibTeX, pdf.
Simulators are commonly used in embedded system development processes for early functional validation of code and exploration of new instruction set design. Such a simulator can be either hand-written or generated automatically, based on an Hardware Architecture Description Language. Automatically generated simulators are more maintainable and are faster to develop, but they also generally suffer from low performances in simulation speed and a lack of expressivity in the description.
This paper presents how a cycle accurate simulator is generated automatically from a description written using the Harmless language. It differs from other hardware description languages in many ways: it resolves most expressivity issues and naturally offers a flexible description by explicitly splitting the syntax (mnemonic), format (binary code) and behavior descriptions. Thus, it allows an incremental description, starting for example by the disassembler (requiring format and syntax descriptions). When the first two descriptions are validated, the behavior description is added to obtain the instruction set simulator. Finally, the micro-architecture description adds information to build a cycle accurate simulator.
@inproceedings{KBBTS-MESM-09,
Author = {Rola Kassem and Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet and Guillaume Savaton},
booktitle = {International Middle Eastern Multiconference on Simulation and Modelling (MESM'09), Eurosis, Beirut, Lebanon},
Title = {Cycle Accurate Simulator Generation Using HARMLESS},
Month = {September},
Year = {2009}}
}
[KBBST-SIMUTOOLS-09]
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton and Yvon Trinquet. Instruction Set Simulator Generation Using HARMLESS, a New Hardware Architecture Description Language. 2nd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2009, Rome, Italy, March 2-6, 2009. ICST 2009Abstract, BibTeX, pdf.
Instruction set simulators are commonly used in embedded system development processes for early functional validation of code and exploration of new instruction set design. Such a simulator can be either hand-written or generated automatically, based on an Hardware Architecture Description Language. Automatically generated simulators are more maintainable and are faster to develop, but they also generally suffer from low performances in simulation speed and a lack of expressivity in the description.
This paper introduces Harmless, a new language to generate automatically instruction set simulators. It differs from other languages in many ways: it resolves most expressivity issues and naturally offers a flexible description by explicitly splitting the syntax (mnemonic), format (binary code) and behavior descriptions. Thus, it allows an incremental description, starting for example by the disassembler (requiring format and syntax descriptions). When the first two descriptions are validated, the behavior description is added to obtain the simulator. Some results are also presented on the simulator build process, specially on the decoder generation. An instruction cache is also introduced to speed up simulation in the same order of magnitude than hand-written simulators. Some experimental results are eventually presented.
@inproceedings{KBBST-SIMUTOOLS-09,
Author = {Rola Kassem and Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Guillaume Savaton and Yvon Trinquet},
Booktitle = {2nd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2009},
Month = {march},
Title = {Instruction Set Simulator Generation Using HARMLESS, a New Hardware Architecture Description Language},
Year = {2009}}
[KBBST-IMCSIT-08]
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton and Yvon Trinquet. Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis. International Multiconference on Computer Science and Information Technology (IMCSIT'08), october 2008, Wisla, PolandAbstract, BibTeX, pdf.
Hardware simulation is an important part of the design of embedded and/or real-time systems. It can be used to compute the WCET and to provide a mean to run software when final hardware is not yet available. Building a simulator is a long and difficult task, especially when the architecture of processor is complex. This task can be alleviated by using a Hardware Architecture Description Language and generating the simulator.
In this article we focus on a technique to generate an automata based simulator from the description of the pipeline. The description is transformed into an automaton and a set of resources which, in turn, are transformed into a simulator. The goal is to obtain a cycle-accurate simulator to verify timing characteristics of embedded real-time systems. An experiment compares an Instruction Set Simulator with and without the automaton based cycle-accurate simulator.
@inproceedings{KBBST-IMCSIT-08,
Author = {Rola Kassem and Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Guillaume Savaton and Yvon Trinquet},
Booktitle = {International Multiconference on Computer Science and Information Technology (IMCSIT'08)},
Month = {October},
Title = {Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis},
Year = {2008}}
[BBFT-ETFA-06]
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou and Yvon Trinquet. Trampoline - An OpenSource Implementation of the OSEK/VDX RTOS Specification. 11th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'06), september 2006, Prague, Czech Republic.Abstract, BibTeX, pdf.
This paper introduces an OSEK/VDX Operating System implementation. OSEK/VDX is an industry standard for real-time operating system used in the field of automotive embedded software. This implementation is proposed in the context of the open source software, which interest needs not to be demonstrated any more. The paper explains the main implementation choices as well as the technique proposed for the generation of a real-time application. This implementation is nowadays available for three targets: Infineon C167, Darwin/PowerPC and Linux/x86.
@inproceedings{BBFT-ETFA-06,
Author = {Jean-Luc B{\'e}chennec and Mika{\"e}l Briday and S{\'e}bastien Faucou and Yvon Trinquet},
Booktitle = {11th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'06)},
Month = {september},
Title = {Trampoline - An OpenSource Implementation of the OSEK/VDX RTOS Specification},
Year = {2006}}
[BBT-ETFA-05]
Mikaël Briday, Jean-Luc Béchennec and Yvon Trinquet. Task Scheduling Observation and Stack Safety Analysis in Real Time Distributed Systems Using a Simulation Tool, 10th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'05), september 2005, Catane, Italia.Abstract, BibTeX, pdf.
This paper presents the ReTiS simulation tool and its use for real-time application analysis. Simulation concerns the operational architecture and takes into account the software (executable code of real-time tasks and real-time operating system) and the hardware (set of processors and networks). In this paper we show a mechanism that allows to detect task switch and to analyze task's stack (usage and corruption). This mechanism neither requires any application nor operating system code modification. We show its interest for the analysis of the temporal behavior of real-time applications in a distributed system.
@inproceedings{BBT-ETFA-03,
author = {Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
title = {Task Scheduling Observation and Stack Safety Analysis in Real Time Distributed Systems Using a Simulation Tool},
booktitle = {10th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'05)},
year = {2005},
month = {september}
}
[BBT-RTS-05]
Mikaël Briday, Jean-Luc Béchennec and Yvon Trinquet. Analyse de systèmes temps réel distribués par simulation : observation des tâches et des piles, 13th International Conference on Real-Time Systems (RTS'05),Paris, France.Abstract, BibTeX, pdf.
Cet article présente quelques concepts de l'outil de simulation ReTiS, dédié à l'analyse d'applications temps réel distribuées. La simulation prend en compte l'architecture opérationnelle: l'architecture matérielle (processeurs, réseaux, ...) et l'architecture logicielle (code applicatif et code système). L'analyse exploite une modélisation fine de l'architecture matérielle (simulateur de jeu d'instruction ou simulateur au niveau cycle) et permet de reconstruire l'ordonnancement des tâches et l'usage des pile en se fondant sur l'observation des événements bas niveau de simulation. Cette observation est basée sur un mécanisme générique: l'action, traitement de l'événement observé. Ce mécanisme ne nécessite aucune modification du code applicatif ou système.
@inproceedings{BBT-RTS-03,
author = {Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
title = {Analyse de systèmes temps réel distribués par simulation : observation des tâches et des piles},
booktitle = {Proceedings of 13th International Conference on Real-Time Systems (RTS'05)},
year = {2005},
month = {April}
}
[BBT-WFCS-04]
Mikaël Briday, Jean-Luc Béchennec and Yvon Trinquet. ReTiS: a Real-Time Simulation Tool for the Analysis of Distributed Real-Time Applications, 5th IEEE International Workshop on Factory Communication Systems (WFCS'04), pages 257-264, september 2004, Vienna, Austria.Abstract, BibTeX, pdf.
This paper presents a simulation tool for real-time applications analysis. Simulation concerns the operational architecture and takes into account the executable code of real-time tasks and the execution support model: set of processors, network and basic software (real-time executive and communication system). We show in this paper a mechanism allowing to track data transfers and its interest for the analysis of the temporal behavior of real-time programs in a distributed system.
@inproceedings{BBT-WFCS-04,
author = {Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
title = {ReTiS: a Real-Time Simulation Tool for the Analysis of Distributed Real-Time Applications},
booktitle = {5th IEEE International Workshop on Factory Communication Systems. WFCS'04},
year = {2004}
}
[BBT-FET-03]
Mikaël Briday, Jean-Luc Béchennec and Yvon Trinquet. Modelisation of a distributed hardware system for accurate simulation of real-time applications, 5th IFAC conference on fieldbus and their applications (FET 2003), pages 37-44, july 2003, Aveiro, Portugal. Elsevier Science.Abstract, BibTeX, pdf.
This paper presents a validation approach for real-time applications using simulation techniques. Simulation concerns the operational architecture and takes into account the executable code of real-time tasks and the execution support model: set of processors, network and basic software (real-time executive and communication system). We show in this paper the performances that can be reached for the analysis of the temporal behaviour of real-time programs in a distributed system.
@inproceedings{BBT-FET-03,
author = {Mika{\"e}l Briday and Jean-Luc B{\'e}chennec and Yvon Trinquet},
title = {Modelisation of a Distributed Hardware System for Accurate Simulation of Real Time Applications},
booktitle = {Proceedings of 5th IFAC International Conference on Fieldbus Systems and their Applications (FeT'03)},
year = {2003},
month = {july}
}

Talks

[BBFMT-CNRIUT-09]
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Pierre Molinaro and Yvon Trinquet. Trampoline : un support pour le développement d'applications temps réel, 15ème Colloque National de la Recherche en IUT (CNRIUT'09), juin 2009, Lille, FranceAbstract, BibTeX, pdf.
Cet article présente une chaîne de développement logiciel, pour les systèmes embarqués temps réel, s'appuyant sur le standard OSEK/VDX de l'automobile. L'article a pour objectif de montrer comment des développements effectués dans le contexte recherche ont pu être réutilisés pour l'enseignement en IUT GEII, suite à l'évolution du Programme Pédagogique National il y a quelques années. La suite d'outils permet à partir d'une conception initiale d'architecture logicielle sous forme de tâches et d'ISR de mettre en oeuvre l'application temps réel à l'aide de seulement deux fichiers : l'un pour décrire l'architecture applicative par description des objets (tâches, ISRs, alarmes, événements ...) en langage standard OIL, l'autre pour décrire les actions algorithmiques des tâches et ISRs en langage C. Diverses implémentations de l'exécutif temps réel permettent de travailler sur cible microcontrôleur (C167, ARM7, MPC565, H12, AVR ...) ou bien sur cible Posix. L'ensemble de la chaîne est disponible sous forme de logiciel libre.
@inproceedings{BBFMT-CNRIUT-09,
Author = {Jean-Luc B{\'e}chennec and Mika{\"e}l Briday and S{\'e}bastien Faucou and Pierre Molinaro and Yvon Trinquet},
Booktitle = {15{\`e}me Colloque National de la Recherche en IUT (CNRIUT'09)},
Month = {June},
Title = {Trampoline : un support pour le d{\'e}veloppement d'applications temps r{\'e}el},
Year = {2009}}

Ph.D Thesis

[Briday-PhD-04]
Mikaël Briday. Validation par simulation fine d'une architecture opérationnelle. Thèse de doctorat de l'université de nantes, 10 decembre 2004. Abstract, BibTeX, pdf.
@book{Briday-PhD-04,
author = {Mika{\"e}l Briday},
title = {Validation par simulation fine d'une architecture op\'erationnelle},
booktitle = {Th\`ese de doctorat de l'Universit\'e de Nantes.},
year = {2004}
}

La validation des systèmes temps réels est une activité indispensable car les conséquences d'une erreur peuvent être catastrophiques. L'approche choisie dans cette thèse se situe en fin du cycle de développement, lorsque le logiciel applicatif est disponible. L'objectif visé est la simulation d'une architecture opérationnelle comprenant une architecture matérielle décrite finement (processeurs et réseaux) et une architecture logicielle connue (indirectement) au travers des programmes exécutables (code applicatif et code système).

Une contribution importante de la thèse se situe dans les mécanismes génériques d'extraction d'informations à partir de la simulation "bas niveau" du code assembleur des programmes, pour en déduire des informations "haut niveau" exploitables par le concepteur. L'étude s'est focalisée sur l'étude du flot de données, l'analyse de l'ordonnancement du code final de l'application ainsi que l'analyse de la pile associée à chaque tâche, à travers l'outil ReTiS.

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