Modeling and simulation of hardware execution plateforms for real-time systems
The goal is to model and simulate efficiently and accurately a hardware plateform. The simulator is able to execute the actual binary code of a real time application and provide an accurate execution time of the simulated software. To model the plateform, we are developing a Hardware Architecture Description Language called HARMLESS. From the HARMLESS description, a compiler generates an Instruction Set Simulator (ISS) or a Cycle Accurate Simulator (CAS). The CAS uses an automaton based model to simulate efficiently the pipeline of the processor. We work, Mikaël Briday and I, since 2006 on this topic and Rola Kassem defended its PhD thesis on 2010.
Further work includes the extension to multicore architectures, the extension to superscalar architectures and performance improvement.
We collaborate with Guillaume Savaton from ESEO.
Real-time operating systemsTrampoline had been developed in this topic and is now a mature real time operating system. Further work in this topic includes:
- Multiprocessor/multicore implementation. The design will be proved with a model checker and it will allow to change the scheduler;
- Generation of the scheduler and part of the API using a DSL.
Both topics are currently supported by ANR RESPECTED
WCET computation using program slicing and real-time model checking
- An Architecture Description Language for Embedded Hardware Platforms. In International Workshop on OCL and Textual Modelling (OCL 2011) June 2011.
- Extending HARMLESS Architecture Description Language for Embedded Real-Time Systems Validation. In 6th IEEE International Symposium on Industrial Embedded Systems (SIES’11) June 2011.
- Viper: a lightweight approach to the simulation of distributed and embedded software. In 3rd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2010 (acceptance rate 29%), March 2010.
- Instruction set simulator generation using harmless, a new hardware architecture description language. In 2nd International Conference on Simulation Tools and Techniques for Communications, Networks and Systems, SimuTools 2009 (acceptance rate 39%), March 2009.
- Cycle accurate simulator generation using Harmless. In International Middle Eastern Multiconference on Simulation and Modelling (MESM'09), Eurosis, Beirut, Lebanon, September 2009.
- Simulator generation using an automaton based pipeline model for timing analysis. In International Multiconference on Computer Science and Information Technology (IMCSIT'08), October 2008.
- Trampoline - an opensource implementation of the OSEK/VDX rtos specification. In 11th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'06)}, September 2006.
- Retis: A real-time simulation platform. Journal Européen des Systèmes Automatisés (JESA), 40(8):819 to 846, 2006.
- I am the project leader of Trampoline, a real-time operating system compliant with the OSEK/VDX standard and with the AUTOSAR standard. Trampoline is Free Software. Trampoline is distributed as a commercial product in the AUTOSAR Basic Software offer of See4sys. Current Trampoline developers are Sébastien Faucou, Mikaël Briday, Jonathan ILIAS (ESEO) and peoples from See4sys.
- I work with Mikaël Briday on HARMLESS, a Hardware Architecture Description Language
Check RTS Software for other software from the Real Time System Group.